1. Field of the Invention
The present invention relates generally to integrated circuit clocking and, more specifically, the present invention relates to optical clock distribution networks in integrated circuits.
2. Description of the Related Art
An issue facing the integrated circuit industry today is the problem of distributing clock signals throughout an integrated circuit die with low clock skew. Clock skew is the difference in arrival times of clock edges to different parts of the chip. Synchronous digital logic requires precise clocks for the latching data. Ideal synchronous logic relies on clocks arriving simultaneously to all the circuits. Clock skew reduces the maximum operating frequency of the circuit as the circuit has to be designed for worst case skew for it to operate reliably. The principle cause of clock skew in the global clock distribution of an integrated circuit is the variation in the routing impedance of the clock distribution within the die. Hence clock skew arises even with an equal length clock distribution network such as an H-Tree. A good rule of thumb in the industry is that clock skew budget is approximately 10% of the cycle time. Hence for a 1 GHz clock frequency, which corresponds to a 1 ns cycle time, the tolerable clock skew is less than or equal to 100 ps. As VLSI clock frequencies increase beyond 1 GHz, the requirement on the clock skew becomes more challenging.
In today's prior art global clock distribution network clock skew is controlled by the use of hierarchical H-trees. FIG. 1A is a diagram illustrating such a hierarchical H-tree clock distribution network 101 that is implemented in high speed integrated circuits to reduce or eliminate the clock skew effect. As shown in FIG. 1A, a clock driver 103 is used to drive H-tree network 101 at the center node 105. It is appreciated that clock driver 103 is typically a very large driver in order to provide sufficient drive to H-tree network 101, which typically has a large capacitance in today's complex high speed integrated circuits. As can be observed in FIG. 1A, the clock paths of the "H" formed between nodes 107, 109, 111 and 113 have equal lengths between center node 105 and each of the peripheral points of the "H" at nodes 107, 109, 111 and 113. Therefore, assuming a uniform propagation delay of a clock signal per unit length of the H-tree network 101, there should be no clock skew between the clock signal supplied to nodes 107, 109, 111 and 113 from clock driver 103.
FIG. 1A further illustrates H-tree network 101 taken to another hierarchical level with an "H" coupled to each respective peripheral node of the first level "H." Accordingly, every peripheral node 115 is an equal distance from node 107. Every peripheral node 117 is an equal distance from node 109. Every peripheral node 119 is an equal distance from node 111. Finally, every peripheral node 121 is an equal distance from node 113. Therefore, the clock paths from all nodes labeled 115, 117, 119 and 121 are an equal distance from clock driver 103 and therefore should have no clock skew between them since the clock delay from clock driver 103 should be equal to all peripheral nodes of the H-tree network 101. Thus, each node 115, 117, 119 and 121 can be configured to act as a receiving station for a clock signal and service the clocking requirements of an area of the integrated circuit near the node with negligible clock skew with reference to the other similarly configured nodes of the H-tree network 101.
As integrated circuits continue to become larger, more complex and run at higher frequencies, clock skew continues to be a challenging issue, even with an H-tree network 101 since the H-tree network 101 clock lines do not always have uniform characteristic impedance. As a result, there may be a non-uniform propagation delay of a clock signal traveling through the paths H-tree network 101 even though nodes 115, 117, 119 and 121 are in equal distance from clock driver 103. Consequently, there is an unpredictable clock skew at the end points of the H-tree clock distribution network 101.
In addition to clock skew the clock distribution on the chip consumes valuable routing resources in integrated circuits that could be better used for signals and thereby improve signal routability. An additional concern integrated circuit designers must consider is that prior art global clock distribution networks also consume an increasing amount of integrated circuit die area as well as power. For instance, the global clock distribution on today's high speed integrated circuit chips typically accounts for approximately 10% of the chip power.
Other prior art techniques of distributing clock signals throughout an integrated circuit have been investigated. Some of these prior art techniques include an optical clock distribution network 151 illustrated in FIG. 1B. An off chip optical source 153 generates an optical clock signal 155 which is split with hologram 157 into split beams 159 and 161. A direct line of sight is provided to the detectors 163 and 165 from the front side surface 179 of integrated circuit die 171 to receive split beams 159 and 161 respectively. Clock signal 167 is generated by detector 163 and clock signal 169 is generated by detector 165. Since the clock signal is then locally distributed from the detectors 163 and 165 using on chip metal interconnects clock signals 167 and 169 are available to clock their respective areas of the integrated circuit.
A major difficulty with the prior art optical clock distribution is the difficulty in implementing it for advance packaging technologies such as Control Collapse Chip Connection (C4) packaged chips (sometimes referred to as flip chip) and C4/MCM (multi chip modules). FIG. 2B is an illustration of a C4 packaged chip 251. C4 is the packaging of choice for future high frequency chips as it provides high density low inductance connections using ball bonds 153 between chip 255 and package 261 by eliminating the high inductance bond wires as are used in today's wire bond packages. FIG. 2A is an illustration of a chip 201 using today's wire bond packages. As shown in FIG. 2A, wire bonds 203 are used for connections between package 211 and chip 205. For C4 packaging, the front side of the chip is no longer accessible and with the prior art optical routing, the routing would need to be integrated into the package itself. This places extremely complex constraints on the design of the C4 substrate which now has to have both electrical and optical routing.
Another important problem with the prior art optical distribution network 151 is that the requirement of locating detectors 163 and 165 in the line of sight of split beams 159 and 161 from the front side surface 179 of integrated circuit 171 is a challenging task with modern integrated circuits which typically utilize five or more metal interconnect layers. With the stacking of a large number of metal interconnect layers, creating a line of sight between the split beams 159 and 161 and detectors 163 and 165, without incurring routing congestion becomes an extremely challenging task. This is because line of sight implies that there should be no metal routing at any level of interconnect above the P-N junction detectors. Hence the P-N junction detectors become routing obstacles and as the number of detectors increases this leads to an increase in the die size which generally reduces manufacturing yields and performance.
Thus, what is needed is a clock distribution network that overcomes the problems of the prior art. Such a clock distribution network would provide minimal clock skew to high speed, high power integrated circuits packaged into C4 (flip chip) and C4/MCM packaging and be fully compatible with the back side heat sink attachment for these packages. Secondly, the clock distribution network should reduce the power dissipation due to global clock distribution by eliminating the large capacitive load of the global network. In addition, such a clock distribution network should not interfere with on chip signal routing and would be able to provide low skew clock distribution as integrated circuit chips increase in size, complexity and operate at increasing clock frequencies.